Low Power Full Adder Circuit Design Using Two Phase Adiabatic Static CMOS Logic
نویسنده
چکیده
Adiabatic logic is used to minimize the energy loss during operation of the circuit. Using two-phase adiabatic static CMOS logic (2PASCL) the power consumption can be reduced. This paper compares the power consumption of Static Energy Recovery Full Adder(SERF) and the proposed full adder using two phase adiabatic static CMOS logic(2PASCL). The average power consumption of proposed full adder is 4.8pW which is very less in a comparative study with SERF. The result of this work focuses on the reduction of power consumption with the scaling down technology. KeywordsAdiabatic Logic, 2pascl, Low Power, Full Adder, Static Energy Recovery Logic.
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تاریخ انتشار 2017